7 / 7 checkedResponsesUNKNOWNInspect metric contract
18 cyclesTrace lengthUNKNOWNInspect metric contract
0 failuresAssertionsUNKNOWNInspect metric contract
SIMULATION / SRAM_CONTROLLER_PROTOCOL_001
SRAM controller protocol trace
SRAM Controller
Replay the verified transaction trace that turns read/write requests into one-cycle checked responses.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Follow request acceptance at the clock edge.
- Compare write and read response timing in the saved trace.
- Use the protocol contract to keep analog cell timing separate from RTL behavior.
RUN CARD
Conditions before conclusions.
The browser replays saved RTL evidence. It does not compile or run arbitrary HDL.
Primary knobs
- Memory depth: 8 words
- Data width: 8 bits
- Response contract: one cycle after accepted request
- Checks: self-checking testbench and lint pass
Saved outputs
- transaction trace
- response checks
- RTL source
- VCD waveform
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/sram-controller-web-v1.json
Open file ->RTL source
/data/sram-controller.sv
Open file ->Testbench
/data/sram-controller-tb.sv
Open file ->Waveform VCD
/data/sram-controller.vcd
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Capture every accepted request and expected response.
Keep this method attached when reusing the figure or metric.
Compare read data against the testbench reference model.
Keep this method attached when reusing the figure or metric.
Preserve the VCD and source files with the public replay.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
Educational inferred-register SRAM, not a foundry memory macro.
Carry this boundary into any derivative note, paper draft, or slide.
Protocol timing evidence does not prove analog bitcell access, setup, hold, or array timing.
Carry this boundary into any derivative note, paper draft, or slide.
No synthesis, place-and-route, STA, or macro compiler view is included.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
The dataset records seven checked responses with zero failures.
SRAM_CONTROLLER_PROTOCOL_001
RTL, testbench, and VCD files are downloadable.
SRAM_CONTROLLER_PROTOCOL_001
The linked lab exposes the transaction trace for review.
SRAM_CONTROLLER_PROTOCOL_001
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.