Replay timing before STA.
One primitive, many consequences.

This lab keeps FO4 delay, switching energy, leakage, and EDP together as a bridge from circuit intuition to digital timing evidence.

REPLAY CARD

Delay, energy, and leakage are different claims.

The FO4 card is intentionally small, because it teaches the condition card every larger timing result will need later.

SA-DIG-001-FO4-TIMING-001

Replay VDD and temperature to connect standard-cell delay, switching energy, leakage, and an EDP-style index.

Use FO4 as a bridge from inverter intuition to standard-cell timing.
Read delay, energy, and leakage together before optimizing only VDD.
Treat this as a timing vocabulary card before Liberty, STA, and OpenROAD artifacts.

SA-EDA-STA-001

Replay VDD, temperature, load, and path depth to connect Liberty-style delay terms with setup slack, hold slack, and timing-report criticality.

No arbitrary HDL compile, Liberty generation, STA signoff, PDK ingestion, upload, account, payment, comment, or product-release workflow is enabled.