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SASemiAgoraSemiconductor knowledge & engineeringOpen replay lab

LESSON PACKET / SA-DIG-001

Timing starts with a primitive.
FO4 makes delay tangible.

This packet turns FO4 into a precomputed timing card before STA: VDD, temperature, delay, energy, leakage, and EDP are kept in one evidence surface.

primitiveFO4 DelayobjectRun CardpolicyBoundaries

FO4 TIMING

A tiny delay card can discipline a large timing conversation.

Before library characterization, OpenROAD flow reports, or STA path evidence, FO4 gives a learner a concrete vocabulary for VDD, temperature, delay, energy, and leakage.

SA-DIG-001-FO4-TIMING-001

FO4 delay and energy scaling

Replay VDD and temperature to connect standard-cell delay, switching energy, leakage, and an EDP-style index.

23.6891.2 V / -20 C20 cases
Open simulation ->
SA-EDA-STA-001

STA Liberty path slack replay

Replay VDD, temperature, load, and path depth to connect Liberty-style delay terms with setup slack, hold slack, and timing-report criticality.

-341.266 ps-14.47 ps81 cases
Open simulation ->

Next evidence step

The correct next upgrade is not live arbitrary HDL. It is an artifact-based timing ladder: standard-cell sizing, Liberty condition cards, OpenROAD reports, and STA path replay.

Open digital roadmap ->

Public boundary

No Liberty characterization, arbitrary synthesis, STA service, PDK ingestion, live SPICE, upload, account, payment, comment, or signoff workflow is active. This is a precomputed timing primitive.

Open Digital domain ->