38.17%Largest current errorUNKNOWNInspect metric contract
80 kohm / 0.1 VWorst caseUNKNOWNInspect metric contract
36 casesSweep rowsUNKNOWNInspect metric contract
SIMULATION / SA-SEED-CIR-MIRROR-COMPLIANCE-001
Current mirror compliance and output resistance
Mirror Compliance
Replay output voltage and output resistance to see when a current mirror stops behaving like a current source.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Move output voltage toward the compliance edge and watch current-source behavior collapse.
- Compare output resistance before blaming only mismatch.
- Use the card as a practical analog-design bridge before SPICE sizing.
RUN CARD
Conditions before conclusions.
This page replays saved current-mirror data and does not run a live SPICE or PDK simulation.
Primary knobs
- Output resistance
- Output voltage
- Compliance voltage
Saved outputs
- Current
- Current error
- Worst-case row
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/current-mirror-compliance-web-v1.json
Open file ->Seed sweep summary CSV
/data/github-open-source-seed-sweep-summary.csv
Open file ->Seed model script
/data/github_open_source_seed_sims.py
Open file ->Seed model card
/data/github-open-source-seed-sims-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Target current is adjusted by finite output resistance and a compliance penalty.
Keep this method attached when reusing the figure or metric.
Current error is measured relative to the nominal target current.
Keep this method attached when reusing the figure or metric.
Worst case is selected by largest absolute current-error percentage.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No transistor sizing, mismatch Monte Carlo, PVT corner, layout parasitic, or BSIM model is included.
Carry this boundary into any derivative note, paper draft, or slide.
No analog IP signoff or production bias recommendation is made.
Carry this boundary into any derivative note, paper draft, or slide.
Use ngspice or Xyce with a public model deck for publishable circuit evidence.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
Seed sweep JSON records output resistance, voltage, current, and error rows.
SA-SEED-CIR-MIRROR-COMPLIANCE-001
CSV export preserves the compliance sweep table.
SA-SEED-CIR-MIRROR-COMPLIANCE-001
GitHub expedition notes Xyce and PySpice as external solver references.
SA-SEED-CIR-MIRROR-COMPLIANCE-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.