Headroom decides whether a mirror still mirrors.
A current mirror is not only a ratio. Output voltage, finite output resistance, and compliance collapse all shape the delivered current.
38.17% worst error / open ->LESSON PACKET / SA-CIR-002
Analog primitives.
Bias before beauty.
This packet adds practical circuit-design cards beside the CMOS inverter lesson: current mirror compliance and sense-regeneration margin. Both stay precomputed until public SPICE evidence is ready.
CONCEPT ARC
Useful analog design starts from conditions.
These are not replacement SPICE decks. They are compact, inspectable run cards for the questions designers repeatedly ask: did I keep enough headroom, and can the circuit decide in time?
Small input differences become timing and yield questions.
Input delta, offset sigma, decision probability, and regeneration time make sense amplifiers and comparators easier to reason about before transistor-level SPICE.
15 cases / open ->SIMULATION BUNDLE
Open the artifact first.
The linked run cards keep methods and limits attached so paper-writing users can cite the boundary before reusing any figure.
Current mirror compliance and output resistance
Replay output voltage and output resistance to see when a current mirror stops behaving like a current source.
Open simulation ->Sense amplifier input delta, offset, and regeneration
Replay input differential, offset sigma, decision probability, regeneration time, and fail-rate proxy for memory and comparator intuition.
Open simulation ->Public boundary
No live SPICE, arbitrary circuit upload, proprietary model deck, account, payment, comment, newsletter signup, or analog IP signoff workflow is active. These are educational precomputed replays.
Open Circuit domain ->