4096synthetic comparison rowsUNKNOWNInspect metric contract
4device architecturesUNKNOWNInspect metric contract
0live server runsUNKNOWNInspect metric contract
SIMULATION / SA-DEV-GAAFET-COMPARISON-002
MOSFET, FinFET, GAAFET, and CFET architecture comparison replay
Device architecture comparison
A browser CSV replay for comparing electrostatic control, footprint, contacts, capacitance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff without turning an architecture roadmap into a universal ranking.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Filter architecture, scaling context, contact strategy, variability mode, circuit context, and review posture before reading any comparison score.
- Compare electrostatic control and drive per footprint with capacitance, contact resistance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff.
- Use the decision gate to find the next missing evidence rather than naming a universal architecture winner.
- Keep the public boundary visible: this is not a calibrated TCAD/compact-model result, node ranking, vendor benchmark, product claim, cost/yield claim, or signoff packet.
BROWSER INTERACTIVE LAB
Filter the saved CSV. Inspect matching replay rows.
No server solver is running here. The browser filters a precomputed table and redraws the plot locally.
Loading replay rowsReading the saved CSV in this browser.
electrostatic control scoredrive per footprint proxycapacitance burden proxycontact resistance burden proxyvariability sensitivity proxyintegration risk proxy
Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.
n/aelectrostatic control score
n/adrive per footprint proxy
n/acapacitance burden proxy
n/acontact resistance burden proxy
n/avariability sensitivity proxy
n/aintegration risk proxy
Change one or more controls to find a saved row. No unrelated CSV value is substituted.
| case id | architecture label | scaling context label | contact strategy label | variability mode label | circuit context label | review posture label | electrostatic control score | drive per footprint proxy | capacitance burden proxy | contact resistance burden proxy | variability sensitivity proxy | thermal coupling proxy | integration risk proxy | circuit handoff readiness score | comparison readiness score | decision gate | next safe check |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Loading saved replay rows... | |||||||||||||||||
RUN CARD
Conditions before conclusions.
The browser filters saved CSV rows. It does not run TCAD, SPICE, compact-model fitting, extraction, electrothermal or process simulation, uploaded design parsing, node ranking, qualification, or server-side models.
Primary knobs
- architecture
- scaling context
- contact strategy
- variability mode
- circuit context
- review posture
Saved outputs
- electrostatic-control score
- drive-per-footprint proxy
- capacitance-burden proxy
- contact-resistance-burden proxy
- variability-sensitivity proxy
- thermal-coupling proxy
- integration-risk proxy
- evidence-maturity score
- circuit-handoff readiness
- comparison-readiness score
- decision gate
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Device architecture comparison CSV
/data/mosfet-finfet-gaafet-cfet-architecture-comparison-replay-v91.csv
Open file ->Typed web JSON
/data/mosfet-finfet-gaafet-cfet-architecture-comparison-replay-web-v1.json
Open file ->Model card
/data/mosfet-finfet-gaafet-cfet-architecture-comparison-replay-model-card-v1.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Generate a Cartesian synthetic sweep across four architectures, four scaling contexts, four contact strategies, four variability modes, four circuit contexts, and four review postures.
Keep this method attached when reusing the figure or metric.
Compute normalized educational proxies with architecture-specific interactions for fin quantization, GAA gate-stack sensitivity, CFET vertical alignment, and contact-context compatibility.
Keep this method attached when reusing the figure or metric.
Apply decision gates that prioritize context compatibility, source/evidence maturity, electrostatics, parasitics, variability, thermal coupling, integration, and device-to-circuit handoff before bounded comparison.
Keep this method attached when reusing the figure or metric.
Store CSV, typed JSON, model card, source links, and public boundary together without copied decks, models, layouts, process flows, measurements, tables, figures, or vendor benchmarks.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No live TCAD, SPICE, compact-model fitting, parasitic extraction, electrothermal solving, process simulation, or architecture optimizer runs in the browser or on the server.
Carry this boundary into any derivative note, paper draft, or slide.
No PDK, compact model, TCAD deck, process flow, layout, extraction technology file, standard-cell library, measured silicon, vendor benchmark, roadmap table, or source figure is copied.
Carry this boundary into any derivative note, paper draft, or slide.
No architecture, foundry node, vendor, product, or process is ranked; no signoff, qualification, readiness, cost, yield, or production recommendation is made.
Carry this boundary into any derivative note, paper draft, or slide.
Rows are original normalized teaching proxies. Engineering reuse requires owned calibrated device models, I-V/C-V, geometry and variability metrology, contact/local-RC extraction, thermal evidence, circuit correlation, and cross-domain owner review.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
CSV replay with 4096 rows and explicit architecture, context, metric, decision-gate, evidence-state, next-check, and teaching-readout fields.
SA-DEV-GAAFET-COMPARISON-002
Typed JSON summary with axes, source anchors, gate counts, contextual architecture averages, example rows, and no-ranking boundary.
SA-DEV-GAAFET-COMPARISON-002
Model card and link-only source spine saved beside the public dataset and canonical experiment record.
SA-DEV-GAAFET-COMPARISON-002
Sources are official/public research, roadmap, metrology, and technology pages used as outbound anchors only; no external body text, figures, tables, models, layouts, measurements, or code is copied.
SA-DEV-GAAFET-COMPARISON-002
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
IBM Research: Toward ultimate scaling of MOSFETResearch metadata anchoring planar-MOSF and FinFET electrostatic comparison vocabulary. No paper body, figure, model, or table is copied.imec: Entering the nanosheet transistor eraOfficial public reading-room article anchoring FinFET-to-GAA nanosheet control, width, capacitance, and variability context.IBM Research: Stacked nanosheet GAA transistorResearch metadata anchoring stacked-nanosheet GAA electrostatics, effective width, and contact vocabulary.imec: A view on the logic technology roadmapOfficial roadmap article connecting FEOL architecture, MOL contacts, local interconnect, routability, and DTCO context.imec: CFET on the logic technology roadmapOfficial public CFET article anchoring monolithic and sequential stacking plus integration-complexity vocabulary.IRDS: More Moore device characteristicsPublic roadmap document anchoring architecture inflection, PPAC, 3D integration, thermal, and metrology context.NIST: Metrology for next-generation semiconductor devicesOfficial publication record anchoring dimensional-metrology and complex-3D-device measurement limits.Synopsys: GAA to CFET transistor scalingOfficial public technology article anchoring planar, FinFET, GAA, and CFET coexistence plus device-to-design handoff vocabulary.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.