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SASemiAgoraSemiconductor knowledge & engineeringOpen run card

LESSON PACKET / SA-DEV-GAAFET-COMPARISON-002

Architecture comparison needs context, not a winner.
Device / Advanced CMOS

Planar MOSFET, FinFET, GAAFET nanosheet, and CFET only become comparable when electrostatic control, footprint, contact and capacitance burden, variability, heat, integration risk, evidence maturity, and circuit handoff stay in one packet.

Open simulationOpen replay lab ->
packetSA-DEV-GAAFET-COMPARISON-002runSimulation ObjectlearnEvidence SequencemethodMethodslimitsBoundaries

EVIDENCE SEQUENCE

What the learner should inspect first.

This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.

01

Start with architecture, scaling context, contact strategy, variability mode, circuit context, and review posture before reading any score.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
02

Compare electrostatic control and drive per footprint with capacitance, contact resistance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
03

Use the decision gate to choose the next evidence check and keep node, vendor, product, cost, yield, and readiness ranking blocked.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->

METHODS

Precomputed model contract.

The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.

method

Original normalized architecture-comparison table based on link-only official public research, roadmap, metrology, and technology vocabulary.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

method

No paper body, figure, roadmap table, compact model, deck, PDK, process flow, layout, extraction file, measured silicon, or vendor benchmark is copied.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

method

The browser filters saved CSV rows and exposes architecture-context, replacement-evidence, no-ranking, and no-live-solver boundaries.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

LIMITS

Useful, but deliberately bounded.

No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.

non-claim

No live TCAD, SPICE, compact-model fitting, extraction, electrothermal, process, optimizer, uploaded design parser, or server-side model.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

non-claim

No PDK, compact model, deck, process flow, layout, extraction technology, measured silicon, architecture/node/vendor/product ranking, signoff, qualification, cost, or yield claim.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

non-claim

Real work needs owned calibrated models, I-V/C-V, short-channel metrics, variability metrology, contact/local-RC extraction, thermal evidence, circuit correlation, and cross-domain owner review.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

SOURCE ANCHOR

Link-only public source spine.

SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.

IBM Research, imec, IRDS, NIST, and Synopsys source spine

https://www.imec-int.com/en/articles/view-logic-technology-roadmap

Open source ->