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SASemiAgoraSemiconductor knowledge & engineeringOpen run card

MEMORY REPLAY LAB / SA-MEM-M3D-IGO-SRAM-004

Carry every tier into the cell and subarray claim.
Memory / Device / Process Integration

A monolithic-3D SRAM claim is not a density sketch. Tier assignment, oxide-semiconductor access transport, contacts, inter-tier connectivity, WL/BL loading, thermal budget, extraction maturity, cell and subarray sensitivities, contradictions, and owned replacement evidence must remain together.

Open simulationStudy lesson ->
packetSA-MEM-M3D-IGO-SRAM-004runSimulation ObjectlearnEvidence SequencemethodMethodslimitsBoundaries

EVIDENCE SEQUENCE

What the learner should inspect first.

This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.

01

Start with the declared tier assignment and access-transport class; neither is a copied topology, layout, process stack, device value, or node claim.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
02

Carry contact burden and inter-tier connection evidence into cell-local, compact-subarray, and routed-subarray WL/BL loading classes.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
03

Keep thermal-budget compatibility and extraction maturity beside every read/write stability, delay, energy, standby, and footprint sensitivity.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
04

Read contradiction flags before reading scores whenever vertical partition, contacts, thermal scope, extraction, routing, or evidence posture disagree.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->
05

End at an owned device, contact, connectivity, thermal, extraction, cell, subarray, variation, measurement, uncertainty, and review gate.

Open the run card to inspect the saved rows, methods, limits, and export files behind this step.

Inspect run card ->

METHODS

Precomputed model contract.

The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.

method

Complete deterministic 4 x 4 x 4 x 4 x 3 x 2 x 2 x 2 Cartesian sweep with no randomness, fitting, hidden data, source-result calibration, or external device value.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

method

Original dimensionless integration, access, contact, inter-tier, thermal, extraction, cell/subarray, delay, energy, footprint, and evidence equations; no TCAD, compact-model, SPICE, SNM, layout, or PEX solver.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

method

Eleven primary, official, roadmap, model-lineage, and metrology anchors are mapped to nine topic-specific nodes while every source topology, parameter, result, percentage, and node claim stays outside the model.

The simulation object keeps the same statement beside downloadable JSON and CSV evidence.

LIMITS

Useful, but deliberately bounded.

No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.

non-claim

No source-reported topology, layout, dimension, device parameter, process condition, extracted parasitic, figure, table, equation, percentage, node claim, or conclusion is copied into the generated rows.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

non-claim

No real PDK, calibrated compact model, TCAD, virtual fabrication, SPICE, SNM extraction, layout, PEX, measured silicon, upload parser, or live server execution.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

non-claim

No architecture winner, material or foundry ranking, product comparison, process recipe, yield forecast, tapeout recommendation, qualification, or signoff claim.

Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.

SOURCE ANCHOR

Link-only public source spine.

SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.

Primary and official M3D Si/oxide-semiconductor SRAM integration source spine

https://arxiv.org/abs/2608.22741

Open source ->