6144deterministic rowsUNKNOWNInspect metric contract
4evidence nodesUNKNOWNInspect metric contract
0live solver runsUNKNOWNInspect metric contract
SIMULATION / SA-DEV-2D-CFET-PPA-003
2D CFET contact-to-parasitic-to-PPA evidence ladder
CFET evidence handoff
Trace original channel and contact hypotheses through local RC, extraction and compact-model maturity, inverter/ring/logic contexts, contradiction flags, and owned replacement evidence before any PPA claim.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Hold transport, parasitic, extraction, compact-model, circuit, voltage, and evidence posture fixed, then sweep the four contact hypotheses in the browser.
- Compare rise/fall delay, equivalent 15-stage frequency, dynamic energy, contact-resistance fraction, layout-capacitance fraction, normalized footprint, and the delay-energy-area product without naming a winner.
- Inspect contradiction flags when a contact-aware row uses an intrinsic-only model or when a layout context is paired with schematic-only extraction.
- Use the decision gate to name the owned contact, device, extraction, circuit, thermal, variation, and review evidence needed to replace each proxy.
BROWSER INTERACTIVE LAB
Filter the saved CSV. Inspect matching replay rows.
No server solver is running here. The browser filters a precomputed table and redraws the plot locally.
Loading replay rowsReading the saved CSV in this browser.
worst delay ps proxydynamic energy fj proxycontact resistance fraction pct proxylayout capacitance fraction pct proxydelay energy area product proxycircuit handoff readiness score
Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.
n/aworst delay ps proxy
n/adynamic energy fj proxy
n/acontact resistance fraction pct proxy
n/alayout capacitance fraction pct proxy
n/adelay energy area product proxy
n/acircuit handoff readiness score
Change one or more controls to find a saved row. No unrelated CSV value is substituted.
| case id | contact hypothesis label | parasitic context label | extraction maturity label | compact model maturity label | circuit context label | contact resistance pair ohm proxy | total switched capacitance ff proxy | worst delay ps proxy | dynamic energy fj proxy | equivalent 15 stage ring frequency ghz proxy | contradiction flags | decision gate | next safe check |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Loading saved replay rows... | |||||||||||||
RUN CARD
Conditions before conclusions.
The browser filters a saved CSV. It does not run quantum transport, TCAD, compact-model fitting, PEX, SPICE, STA, power, thermal, Monte Carlo, upload parsing, or a server solver, and it cannot issue an architecture ranking or PPA signoff.
Primary knobs
- transport asymmetry proxy
- contact-resistance hypothesis
- parasitic context
- extraction maturity
- compact-model maturity
- circuit and supply context
- replacement-evidence posture
Saved outputs
- n/p path resistance and switched-capacitance proxies
- rise/fall delay and equivalent ring-frequency proxies
- dynamic-energy and normalized footprint proxies
- contact and layout-capacitance fractions
- delay-energy-area sensitivity product
- contradiction flags, decision gate, and next owned check
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
2D CFET evidence-ladder CSV
/data/2d-cfet-contact-parasitic-ppa-evidence-ladder-v101.csv
Open file ->Typed web JSON
/data/2d-cfet-contact-parasitic-ppa-evidence-ladder-web-v1.json
Open file ->Model card
/data/2d-cfet-contact-parasitic-ppa-evidence-ladder-model-card-v1.md
Open file ->Metric contract
/data/2d-cfet-contact-parasitic-ppa-evidence-ladder-metric-contract-v1.json
Open file ->Source spine
/data/2d-cfet-contact-parasitic-ppa-evidence-ladder-source-spine-v1.json
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Generate the full deterministic 2 x 4 x 4 x 4 x 3 x 4 x 2 x 2 Cartesian sweep with no random sampling or hidden solver.
Keep this method attached when reusing the figure or metric.
Carry declared channel and contact resistance, extracted local resistance, intrinsic/contact/local/load capacitance, circuit stack/load, and supply factors through first-order RC delay, equivalent ring-frequency, dynamic-energy, and normalized footprint equations.
Keep this method attached when reusing the figure or metric.
Preserve schematic, rule-estimated, geometry-proxy, and corner-envelope extraction states separately from intrinsic-only, contact-aware, and fixed non-ideality model states.
Keep this method attached when reusing the figure or metric.
Emit contradiction flags whenever the declared contact, parasitic, model, extraction, or evidence posture disagrees, then route every row to an owned-evidence replacement check.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
All 6,144 rows and numeric coefficients are original deterministic SemiAgora teaching assumptions; zero external device, contact, parasitic, layout, model, measurement, or PPA value is used.
Carry this boundary into any derivative note, paper draft, or slide.
No A2 feasibility, 2D material readiness, contacted-pitch scaling, architecture winner, foundry comparison, cost/yield forecast, or production recommendation is made.
Carry this boundary into any derivative note, paper draft, or slide.
No quantum transport, TCAD, compact-model fitting, SPICE, ring-oscillator startup, PEX, field solver, STA, power analysis, thermal solve, Monte Carlo, upload parser, or live server execution occurs.
Carry this boundary into any derivative note, paper draft, or slide.
The RC, delay, energy, area, frequency, and readiness fields are bounded sensitivity proxies, not device specifications, timing-library values, extracted design results, or signoff evidence.
Carry this boundary into any derivative note, paper draft, or slide.
A real claim requires owned geometry/material/contact metrology, bias- and temperature-tagged I-V/C-V, calibrated compact models, extraction tech and convergence lineage, circuit/layout correlation, thermal and variation evidence, and accountable cross-domain review.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
6144 rows covering the complete declared Cartesian sweep with no random sampling or hidden state.
SA-DEV-2D-CFET-PPA-003
Four topic-specific claim maps and nine official, primary, roadmap, metrology, benchmarking, and compact-model anchors.
SA-DEV-2D-CFET-PPA-003
Every source-derived scientific result remains outside the numeric model; all generated values are declared SemiAgora assumptions.
SA-DEV-2D-CFET-PPA-003
Independent Cartesian, equation, contradiction, zero-boundary, byte-identity, and SHA-256 verification is required in the canonical experiment folder.
SA-DEV-2D-CFET-PPA-003
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
2D GAA CFET multiscale PPA preprint metadataScope anchor for the contact-to-parasitic-to-circuit evidence chain; all packet numbers remain original SemiAgora assumptions.imec: 2D-material devices in the logic scaling roadmapIntegration, contact, doping, variability, and staged-evidence vocabulary anchor.imec: monolithic CFET stacked bottom and top contactsStacked-contact, frontside/backside access, isolation, and process-window evidence vocabulary anchor.imec: scaling monolithic CFET across logic nodesDevice-to-ring-oscillator PPA handoff and backside-contact scope anchor without importing reported values.imec: logic technology roadmapFEOL/MOL/BEOL, contact resistance, local interconnect, via, routing, and DTCO vocabulary anchor.NIST: IRDS 2024 metrology chapterMeasurement readiness, structure-function linkage, uncertainty, and manufacturability evidence anchor.NIST: reporting and benchmarking emerging FETsGeometry, contact, bias, extraction, and comparison-contract evidence anchor.NIST: 2D interface flatness and contact-region metrologyInterface morphology, contact-region structure, and measurement boundary anchor.UC Berkeley BSIM model familiesCompact-model provenance and replacement-model boundary anchor.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.