Start with technology, placement target, integration context, workload context, and decision priority before reading a fit score.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->MEMORY REPLAY LAB / SA-MEM-EMERGING-TAXONOMY-003
Emerging memory is a placement decision, not a winner-take-all list.
Memory / Emerging Memory
MRAM, FeFET, ReRAM, PCM, 3D NAND, HBM, eDRAM, SCM, embedded NVM, SRAM, DRAM, and CIM only make sense when placement target, workload, integration burden, reliability evidence, and public boundary stay in the same table.
EVIDENCE SEQUENCE
What the learner should inspect first.
This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.
Compare latency, density, endurance, retention, write energy, read margin, process compatibility, thermal/process risk, integration risk, evidence maturity, and placement score together.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->Use the decision gate to separate shortlist candidates from endurance, retention, read-margin, thermal/process, integration, or poor-fit review.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->METHODS
Precomputed model contract.
The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.
Original synthetic emerging-memory table based on public memory-course, imec, MRAM, and open-access NVM review vocabulary.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
No product ranking, publisher figure, review table, course material, COMSOL file, simulator code, vendor benchmark, or proprietary memory data is copied.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
The browser filters saved CSV rows and exposes the model card with no-live-solver and no-qualification boundaries.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
LIMITS
Useful, but deliberately bounded.
No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.
No live TCAD, SPICE, Ramulator, DRAMsim, COMSOL project, compact-model calibration, product benchmark, or memory-stack optimizer.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
No foundry qualification, product recommendation, vendor ranking, reliability signoff, package stack approval, or technology winner claim.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
Real work needs owned measured cell, array, endurance, retention, read-margin, write-energy, thermal, integration, ECC/verify, and workload evidence.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
SOURCE ANCHOR
Link-only public source spine.
SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.
Purdue Semiconductor Memory 101
https://engineering.purdue.edu/online/semiconductors/semiconductor-memory-101
Open source ->