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SASemiAgoraSemiconductor knowledge & engineeringOpen lesson

SIMULATION / SA-PTR-TEST-WAFER-SORT-001

Wafer sort binning and guardband
Wafer Sort

Replay a teaching guardband tradeoff between yield, top bin, estimated escapes, and retest load.

sectionExploresectionRun CardsectionExportsectionMethodssectionLimitssectionEvidence

EXPLORE

Start with the observable.

Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.

guided exploration
  • Compare minimal, balanced, and aggressive guardband cases.
  • Keep effective yield, top-bin fraction, estimated escapes, and retest load separate.
  • Use the card to ask what characterization and production monitoring would be required next.
Open visual lab ->Open lesson ->

RUN CARD

Conditions before conclusions.

The page replays saved wafer-sort teaching data. It does not generate tester programs, release limits, or submit production test jobs.

precomputed replay

Primary knobs

  • Teaching guardband cases: minimal, balanced, aggressive
  • Outputs: effective yield, top-bin fraction, estimated escape ppm, retest percent
  • Review focus: yield versus quality-risk vocabulary
  • Boundary: no tester program, bin-limit release, production screen, or customer quality statement
outputs

Saved outputs

  • guardband tradeoff table
  • yield ordering check
  • escape ordering check
  • retest ordering check

EXPORT

Download the public artifacts.

These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.

download

Dataset JSON

/data/ptr-wafer-sort-binning-yield-web-v1.json

Open file ->

METHODS

How the number was made.

Methods are written for citation discipline: the extraction rule matters as much as the plotted value.

method

Represent guardband policy as three teaching cases with explicit yield, escape, retest, and binning fields.

Keep this method attached when reusing the figure or metric.

method

Check yield decreases as guardband becomes stricter.

Keep this method attached when reusing the figure or metric.

method

Check estimated escapes decrease while retest load increases.

Keep this method attached when reusing the figure or metric.

method

Keep all production limits, tester code, and customer-quality conclusions outside the public MVP.

Keep this method attached when reusing the figure or metric.

LIMITS

What this page does not claim.

The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.

non-claim

No ATE program, wafer-sort recipe, bin-limit release, production screen, tester-time quote, or outgoing quality claim is included.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

No real distribution, correlation-to-final-test, coverage model, sample size, or shipped-product data is represented.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

The escape ppm field is a teaching proxy and not a quality metric.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

Real reuse requires characterization data, test coverage analysis, production monitoring, quality systems, and qualified owner signoff.

Carry this boundary into any derivative note, paper draft, or slide.

EVIDENCE

Trace the claim back to artifacts.

The evidence route remains the catalog-level browser; this page is the simulation-level reading card.

evidence note

The dataset preserves three guardband teaching cases.

SA-PTR-TEST-WAFER-SORT-001

evidence note

Verification checks yield, escape, and retest ordering.

SA-PTR-TEST-WAFER-SORT-001

evidence note

The model card keeps test-program and production-release boundaries explicit.

SA-PTR-TEST-WAFER-SORT-001

Source spine

These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.

NIST National Advanced Packaging Manufacturing ProgramPublic NIST page framing advanced packaging challenges around power, heat, test, repair, and reliability.SEMI Heterogeneous Integration RoadmapPublic roadmap page connecting assembly, packaging, interconnect, test, thermal management, and reliability.

Public execution boundary

No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.