SEMICONDUCTOR DOMAIN MAP
A role-family sorting spine for turning a growing collection of lessons and simulations into a comprehensive semiconductor platform. This is not the final IA yet; it is the sorting spine for a comprehensive semiconductor site.
DOMAIN CLUSTERS
Each domain shows what is live, what simulation layer is needed next, and which evidence type should keep the claim honest. This lets process, device, circuit, memory, EDA, packaging, and reliability grow without becoming a homepage pile.
High priority because this is the largest missing comprehensive-semi domain on the public site.
Next simulations: Deposition uniformity / Lithography window / Etch selectivity / CMP planarization / Wet clean and native oxide
Evidence: thickness map / CD/overlay / particle/metal proxy / sheet resistance / surface-state metrology
Use as the bridge from individual process modules to real manufacturing reasoning.
Next simulations: DOE response surfaces / SPC capability / defect pareto / split-lot decision tree
Evidence: lot summary / Cp/Cpk / yield pareto / control chart / excursion timeline
Now promoted from placeholder to a static equipment/facilities seed, kept useful for job-family literacy while facility operation and equipment control remain disabled.
Next simulations: cleanroom particle budget / vacuum pumpdown envelope / tool availability state / utilities load budget / EHS boundary vocabulary
Evidence: particle proxy / pumpdown envelope / RAM state table / utility load lane / blocked-operation boundary
Make this the trust layer for every process and device claim.
Next simulations: ellipsometry fit / sheet resistance / CD/overlay / SPC / measurement uncertainty
Evidence: uncertainty / calibration / measurement model / control chart / source standard
The strongest bridge from fundamentals to circuits.
Next simulations: PN junction / MOS capacitor C-V / MOSFET transfer / short-channel concept cards
Evidence: bias sweep / carrier profile / C-V curve / I-V curve / model boundary
Keep as the anchor explainable circuit path.
Next simulations: inverter VTC / propagation delay / ring oscillator / sense amplifier starter
Evidence: DC sweep / transient waveform / PVT note / extraction equation
Maintain as the differentiated memory track.
Next simulations: SRAM read/write/SNM / bitline sensing / DRAM retention / cache behavior
Evidence: shmoo / waveform / fault trace / retention curve / architecture metric
Useful for practice, portfolio, and interview paths.
Next simulations: controller trace / BIST fault replay / ECC injection / waveform reading drills
Evidence: cycle trace / assertion result / fault injection / coverage note
Keep connected to open-source EDA and evidence artifacts.
Next simulations: DRC/LVS/PEX / distributed RC / crosstalk / IR drop / OpenROAD queue
Evidence: GDS / rule result / netlist / timing delta / rail map
Now promoted from backlog to a live PTR seed that completes the front-end-to-product semiconductor story.
Next simulations: package parasitics RLC / thermal resistance stack / wafer-sort guardband / reliability bathtub curve / failure-analysis evidence ladder
Evidence: package parasitic proxy / thermal stack / bin summary / stress-mode table / FA boundary
ROLE FAMILIES
These labels are broad enough for students, researchers, and job seekers, but still technical enough to drive lesson planning.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
Attach lessons, simulations, evidence artifacts, and practice prompts to this family before publishing a bigger collection.
SOURCE SPINE
The source spine keeps the map grounded in current semiconductor role language and measurement discipline. It is a vocabulary anchor, not copied course content.
Public role descriptions used as an external vocabulary anchor for process, integration, equipment, facility, and reliability work.
Open official source ->Public workforce report page used to keep technician, engineering, and advanced-degree talent lanes visible.
Open official source ->Public metrology program page used to keep measurement and standards attached to process, device, and packaging claims.
Open official source ->Public NIST page framing advanced packaging challenges around power, heat, test, repair, and reliability.
Open official source ->Public roadmap page connecting assembly, packaging, interconnect, test, thermal management, and reliability.
Open official source ->Official ISO page anchoring cleanroom air-cleanliness vocabulary by airborne-particle concentration.
Open official source ->Official ISO page anchoring cleanroom requirements, design, construction, start-up, verification, and life-cycle vocabulary.
Open official source ->Official SEMI page anchoring equipment reliability, availability, maintainability, and utilization language.
Open official source ->Official NIST page defining semiconductor materials and manufacturing-equipment facilities for public program vocabulary.
Open official source ->Official ASML page anchoring high-vacuum and precision-wafer-handler vocabulary for EUV tools.
Open official source ->OPERATING BOUNDARY
Career and domain navigation can be useful now while higher-risk workflows stay inactive.
Static role-family navigation / Public source links / Lesson and simulation routing / Evidence-needs backlog
No job board or employer submissions / No user applications or resumes / No account workflow / No private company process data / No facility or recipe workflow