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CIRCUIT / SPICE / EVIDENCE LITERACY

Solver convergence and report literacy

Convergence means the numerical criteria were met for this netlist, model, analysis, and solver configuration. It does not establish numerical refinement, model validity, metric suitability, or signoff.

Original ideal RC step evidence circuit
Original ideal RC teaching circuittau = 1 ns

FIVE INDEPENDENT STATES

One green status cannot color the whole chain.

A simulator can finish while a timestep is too coarse. A refined waveform can use the wrong model. A validated model can still be measured with an incompatible metric. Signoff is a separate governed decision, never an automatic solver output.

01

Solver

Did this netlist, model, analysis, and solver configuration meet its stopping criteria?

02

Numerical

Does a tighter timestep, tolerance, or saved-signal grid keep the scoped result inside declared limits?

03

Model

Has the model been validated for the physical structure and operating range being claimed?

04

Metric

Are the required signals, thresholds, directions, interpolation, units, and limits compatible?

05

Signoff

Has an independent governed review accepted the result for a precisely stated use?

READ IN ORDER

Stop at the first unsupported transition.

PASS, FAIL, and NOT_RUN are evidence states, not confidence colors. NOT_RUN remains visible when a downstream question was never tested.

01Solver

Did this netlist, model, analysis, and solver configuration meet its stopping criteria?

02Numerical

Does a tighter timestep, tolerance, or saved-signal grid keep the scoped result inside declared limits?

03Model

Has the model been validated for the physical structure and operating range being claimed?

04Metric

Are the required signals, thresholds, directions, interpolation, units, and limits compatible?

05Signoff

Has an independent governed review accepted the result for a precisely stated use?

THE V129 COUNTEREXAMPLE

Both runs converge. Only one passes refinement.

The 5 ps reference and 500 ps case both return solver PASS. The coarse case drifts only -0.002558% in mean output, yet its 50% delay moves enough to fail the 0.05% numerical limit and cross the locked 693.4 ps educational decision boundary.

Reference delay
693.146778 ps / numerical PASS
Coarse delay
693.612769 ps / numerical FAIL
Delay drift
0.067228% / limit 0.05%
Mean-output drift
-0.002558% / not a delay substitute
Model validity
NOT_RUN for both
Signoff
NOT_RUN for both

METRIC CONTRACT

The number includes its extraction rule.

V129 locks the start and stop signals, 50% rising thresholds, linear interpolation, picosecond unit, and educational limit. Removing v(in), keeping sparse samples, or switching to first-sample crossing creates a different evidence packet.

01

Signals

v(in) starts; v(out) stops. Missing either signal blocks the metric.

02

Thresholds

Both crossings use 0.5 V on the rising direction.

03

Interpolation

Linear bracketing is not first-saved-sample selection.

04

Saved grid

A 250 ps saved interval can under-resolve a converged waveform.

05

Limit

693.4 ps is an educational check, never a production requirement.

SOURCE SPINE

Methods and numerical-error context

These are link-only anchors. The RC netlists, SVG, replay dataset, decision limit, summaries, and report structure are original SemiAgora teaching artifacts.

ngspice DocumentationOpen source ->ngspice User ManualOpen source ->Berkeley SPICE2 technical reportOpen source ->Xyce Documentation and TutorialsOpen source ->Xyce Users Guide 7.7Open source ->NIST: Errors and uncertainty in numerical simulationOpen source ->KiCad Schematic EditorOpen source ->SemiAgora circuit evidenceOpen source ->
Evidence stop

No proprietary model, extracted interconnect, package, probe, measured calibration, process condition, production limit, qualification, foundry claim, or signoff follows from this original ideal RC example. All thresholds are locked educational evidence checks, not production limits.