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SEMICONDUCTOR KNOWLEDGE ATLAS / 2026-08-31-v116

Map the field.
Follow the evidence.

A public, evidence-aware map from semiconductor foundations through fabrication, devices, circuits, design, measurement, and productization. It shows where public packets exist, where only a source anchor exists, and what should be built next.

THE KNOWLEDGE SPINE

Six connected ways to read the industry.

Start from physics, a wafer step, a device, a circuit, a design artifact, or a measurement decision. The map keeps the handoff visible.

SEARCH / COVERAGE / SOURCES

One atlas, with the gaps left visible.

Search stays in your browser. Results connect taxonomy nodes with public lessons, labs, simulations, evidence routes, domains, and official source links.

45of 45 clusters
225topic nodes in view

Coverage links are cluster-level discovery aids. Open a row to inspect the topic list, evidence need, sources, and next audit.

FM / 001Foundations & Materials / Cross-domain / foundationMathematical & Computational Modeling

Which equation, scale, approximation, and numerical error control the result?

Source anchored
FM / 006Foundations & Materials / Device / foundationCrystal Structure & Semiconductor Materials

How do composition, lattice, and microstructure constrain electronic behavior?

Source anchored
FM / 011Foundations & Materials / Device / foundationQuantum Mechanics & Band Structure

How do allowed states and band alignment shape carrier populations and transitions?

Source anchored
FM / 016Foundations & Materials / Device / intermediateCarrier Statistics & Transport

How do carriers move, scatter, recombine, and produce current?

Public packet
FM / 021Foundations & Materials / Device / intermediateInterfaces, Defects & Surface States

Which interface or defect state changes charge, transport, noise, or reliability?

Evidence reviewed
FM / 026Foundations & Materials / Cross-domain / intermediateThermal Physics & Statistical Mechanics

How do temperature, entropy, and stochastic variation change semiconductor behavior?

Public packet
FI / 031Fabrication & Integration / Process / intermediateSubstrates, Wafers & Epitaxy

How does the starting wafer or grown layer constrain downstream device behavior?

Source anchored
FI / 036Fabrication & Integration / Process / intermediateDeposition & Thin-Film Growth

How do transport and surface reaction become thickness, composition, and conformality?

Evidence reviewed
FI / 041Fabrication & Integration / Process / intermediateLithography & Patterning

How do imaging, resist, focus, dose, and pattern transfer set printed geometry?

Evidence reviewed
FI / 046Fabrication & Integration / Process / intermediateEtch, Plasma & Pattern Transfer

How do plasma chemistry, transport, charging, and selectivity shape the final profile?

Evidence reviewed
FI / 051Fabrication & Integration / Process / intermediateDoping, Implantation & Thermal Processing

How do introduced species and thermal budget become active profiles and defects?

Evidence reviewed
FI / 056Fabrication & Integration / Process / intermediateCleans, Surface Preparation & CMP

How do contamination removal and planarization alter surface readiness and topography?

Evidence reviewed
FI / 061Fabrication & Integration / Process / intermediateContacts, Interconnect & Dielectrics

How do geometry, interfaces, materials, and current density become resistance, capacitance, and reliability?

Evidence reviewed
FI / 066Fabrication & Integration / Equipment / Facilities / advancedIntegration, Equipment & Factory Control

How are unit processes sequenced, monitored, controlled, and handed off without turning teaching content into operating instructions?

Evidence reviewed
DV / 071Devices / Device / intermediateJunction, Diode & Bipolar Devices

How do junction electrostatics and carrier injection create rectification, gain, and breakdown?

Public packet
DV / 076Devices / Device / intermediateMOS Capacitors & Transistors

How do gate electrostatics and transport become threshold, current, capacitance, and leakage?

Evidence reviewed
DV / 081Devices / Device / advancedFinFET, GAAFET & CFET Logic

How do gate control, stacking, contacts, parasitics, and variability trade off across scaled architectures?

Evidence reviewed
DV / 086Devices / Device / advancedPower, SiC & GaN Devices

How do wide-bandgap materials, fields, traps, and thermal paths shape power and RF device limits?

Evidence reviewed
DV / 091Devices / Device / advancedRF & High-Frequency Devices

How do transport, capacitance, parasitics, fixtures, reference planes, and noise limit high-frequency evidence?

Evidence reviewed
DV / 096Devices / Device / advancedPhotonics & Optoelectronics

How do photons, carriers, modes, and materials create emission, detection, and modulation?

Evidence reviewed
DV / 101Devices / Device / advancedSensors & MEMS

How do electrical, mechanical, thermal, chemical, or optical transduction paths become a sensor signal?

Source anchored
DV / 106Devices / Device / advancedEmerging & Quantum Devices

Which state variable stores or transforms information, and what evidence distinguishes a device concept from a product claim?

Source anchored
CS / 111Circuits & Systems / Circuit / intermediateAnalog Circuit Primitives

How do bias, gain, feedback, noise, and loading create an analog response?

Evidence reviewed
CS / 116Circuits & Systems / Digital / Verification / intermediateDigital Logic, Timing & Sequential State

How do logic depth, slew, load, clocking, and state create delay and functional boundaries?

Evidence reviewed
CS / 121Circuits & Systems / Memory / advancedSRAM Cells, Arrays & Periphery

How do transistor ratios, array context, sensing, and assist shape SRAM stability and access?

Evidence reviewed
CS / 126Circuits & Systems / Memory / advancedDRAM, HBM & Memory Hierarchy

How do charge storage, refresh, array organization, and stacked interfaces preserve and move data?

Evidence reviewed
CS / 131Circuits & Systems / Memory / advancedNAND & Emerging Nonvolatile Memory

Which physical state stores information, how is it switched, and what limits retention and endurance?

Evidence reviewed
CS / 136Circuits & Systems / Circuit / advancedMixed-Signal & Data Conversion

How do sampling, quantization, references, mismatch, and timing become conversion accuracy?

Source anchored
CS / 141Circuits & Systems / EDA / Layout / advancedPower, Clock & On-Chip Interconnect

How do delivery networks, switching activity, parasitics, and topology create integrity and timing limits?

Evidence reviewed
CS / 146Circuits & Systems / Digital / Verification / advancedArchitecture, Accelerators & Compute-in-Memory

How do data movement, precision, parallelism, and memory placement shape system efficiency?

Source anchored
DVF / 151Design & Verification / Digital / Verification / intermediateHDL, RTL & Microarchitecture

How is intended cycle-level behavior expressed without hiding reset, latency, and interface contracts?

Public packet
DVF / 156Design & Verification / Digital / Verification / advancedFunctional Verification & Formal Methods

Which behavior is tested, asserted, covered, or proven, and what remains outside the contract?

Source anchored
DVF / 161Design & Verification / EDA / Layout / intermediateLogic Synthesis & Optimization

How do RTL, constraints, libraries, and transforms become a gate-level implementation?

Evidence reviewed
DVF / 166Design & Verification / EDA / Layout / advancedFloorplanning, Placement, CTS & Routing

How do geometry, density, connectivity, power, and clocks become an implementation and its reports?

Evidence reviewed
DVF / 171Design & Verification / EDA / Layout / advancedTiming, Extraction & Signoff Literacy

How do parasitics, constraints, corners, and analysis assumptions become a timing or verification statement?

Evidence reviewed
DVF / 176Design & Verification / Digital / Verification / advancedDFT, BIST & Design for Test

How is internal state made controllable and observable, and which fault model is actually covered?

Public packet
DVF / 181Design & Verification / EDA / Layout / advancedOpen EDA & Reproducible Flows

Can another person identify the exact source, tool, configuration, artifact, and limitation behind the result?

Evidence reviewed
MP / 186Measurement & Productization / Metrology / Yield / intermediateMetrology & Instrumentation

What measurand, instrument chain, sampling plan, and calibration support the reported value?

Evidence reviewed
MP / 191Measurement & Productization / Metrology / Yield / intermediateStatistics, DOE & Uncertainty

How much of the observed variation comes from the process, model, sample, or measurement system?

Evidence reviewed
MP / 196Measurement & Productization / Metrology / Yield / advancedProcess Control, Yield & Defect Learning

Which variation signal warrants monitoring, diagnosis, or action without confusing correlation with root cause?

Evidence reviewed
MP / 201Measurement & Productization / Packaging / Test / Reliability / advancedPackaging, Assembly & Chiplets

How do interconnect geometry, bonding, thermal-mechanical stress, and partitioning affect package readiness?

Evidence reviewed
MP / 206Measurement & Productization / Packaging / Test / Reliability / advancedWafer Sort, Final Test & Characterization

Which test condition, limit, guardband, and coverage support a product decision?

Public packet
MP / 211Measurement & Productization / Packaging / Test / Reliability / advancedReliability & Failure Analysis

Which stress, mechanism, acceleration model, and physical evidence support a lifetime or failure claim?

Evidence reviewed
MP / 216Measurement & Productization / Packaging / Test / Reliability / advancedStandards, Traceability & Quality Systems

Which controlled definition, traceability record, and change history makes the result comparable and auditable?

Source anchored
MP / 221Measurement & Productization / Equipment / Facilities / advancedSafety, Sustainability & Research Data

How are hazards, environmental burdens, data stewardship, and public claims bounded across the lifecycle?

Source anchored
V134 / EVIDENCE KNOWLEDGE GRAPHFollow explicit links from question to stop condition.

Traverse 4,733 nodes, 10,671 declared edges, three guided slices, and every unsupported bridge without automatic graph completion.

Open the graph ->
V131 / COVERAGE & GAP LEDGERInspect all 45 clusters with explicit denominators.

Review source metadata, public experiment links, inherited audit states, gap codes, freshness, and the transparent next-audit queue.

Open the ledger ->

SOURCE & COVERAGE CONTRACT

A map can be broad without pretending to be complete.

Link first, synthesize originally, preserve provenance, and never imply that a registered source has been fully reviewed when only its metadata or index was inspected.

Mapped

A topic and causal question exist. No depth claim follows.

Source anchored

An official or rights-holder link is registered. Exhaustive review is not implied.

Public packet

A related lesson, lab, domain page, or replay exists at cluster level.

Evidence reviewed

A related cluster replay exposes data, methods, limits, and evidence links.

PUBLIC BOUNDARY

What this atlas does not claim.