A topic and causal question exist. No depth claim follows.
SEMICONDUCTOR KNOWLEDGE ATLAS / 2026-08-31-v116
Map the field.
Follow the evidence.
A public, evidence-aware map from semiconductor foundations through fabrication, devices, circuits, design, measurement, and productization. It shows where public packets exist, where only a source anchor exists, and what should be built next.
SEMIAGORA EVIDENCE OS / V140
One question. Five evidence moves.
Start at the stage closest to your work. Every route carries its evidence state, denominator, packet status, and stop condition forward.
0 validated claim-source edges. 384 metric contracts remain UNKNOWN. 3 post-V135 replay exceptions remain explicit.
THE KNOWLEDGE SPINE
Six connected ways to read the industry.
Start from physics, a wafer step, a device, a circuit, a design artifact, or a measurement decision. The map keeps the handoff visible.
Foundations & Materials
What physical model connects material structure and state to an observable?
30 mapped nodesFI / 8 clustersFabrication & Integration
What changed on the wafer, why, and what measurement supports the integration claim?
40 mapped nodesDV / 8 clustersDevices
Which device mechanism creates the measured electrical, optical, thermal, or mechanical response?
40 mapped nodesCS / 8 clustersCircuits & Systems
How does a device or interconnect assumption become a circuit or system observable?
40 mapped nodesDVF / 7 clustersDesign & Verification
What design contract was checked, by which tool and artifact, under which assumptions?
35 mapped nodesMP / 8 clustersMeasurement & Productization
Is the measurement and evidence chain fit for the decision being made?
40 mapped nodesSEARCH / COVERAGE / SOURCES
One atlas, with the gaps left visible.
Search stays in your browser. Results connect taxonomy nodes with public lessons, labs, simulations, evidence routes, domains, and official source links.
Coverage links are cluster-level discovery aids. Open a row to inspect the topic list, evidence need, sources, and next audit.
FM / 001Foundations & Materials / Cross-domain / foundationMathematical & Computational ModelingWhich equation, scale, approximation, and numerical error control the result?
Source anchored
FM / 006Foundations & Materials / Device / foundationCrystal Structure & Semiconductor MaterialsHow do composition, lattice, and microstructure constrain electronic behavior?
Source anchored
FM / 011Foundations & Materials / Device / foundationQuantum Mechanics & Band StructureHow do allowed states and band alignment shape carrier populations and transitions?
Source anchored
FM / 016Foundations & Materials / Device / intermediateCarrier Statistics & TransportHow do carriers move, scatter, recombine, and produce current?
Public packet
FM / 021Foundations & Materials / Device / intermediateInterfaces, Defects & Surface StatesWhich interface or defect state changes charge, transport, noise, or reliability?
Evidence reviewed
FM / 026Foundations & Materials / Cross-domain / intermediateThermal Physics & Statistical MechanicsHow do temperature, entropy, and stochastic variation change semiconductor behavior?
Public packet
FI / 031Fabrication & Integration / Process / intermediateSubstrates, Wafers & EpitaxyHow does the starting wafer or grown layer constrain downstream device behavior?
Source anchored
FI / 036Fabrication & Integration / Process / intermediateDeposition & Thin-Film GrowthHow do transport and surface reaction become thickness, composition, and conformality?
Evidence reviewed
FI / 041Fabrication & Integration / Process / intermediateLithography & PatterningHow do imaging, resist, focus, dose, and pattern transfer set printed geometry?
Evidence reviewed
FI / 046Fabrication & Integration / Process / intermediateEtch, Plasma & Pattern TransferHow do plasma chemistry, transport, charging, and selectivity shape the final profile?
Evidence reviewed
FI / 051Fabrication & Integration / Process / intermediateDoping, Implantation & Thermal ProcessingHow do introduced species and thermal budget become active profiles and defects?
Evidence reviewed
FI / 056Fabrication & Integration / Process / intermediateCleans, Surface Preparation & CMPHow do contamination removal and planarization alter surface readiness and topography?
Evidence reviewed
FI / 061Fabrication & Integration / Process / intermediateContacts, Interconnect & DielectricsHow do geometry, interfaces, materials, and current density become resistance, capacitance, and reliability?
Evidence reviewed
FI / 066Fabrication & Integration / Equipment / Facilities / advancedIntegration, Equipment & Factory ControlHow are unit processes sequenced, monitored, controlled, and handed off without turning teaching content into operating instructions?
Evidence reviewed
DV / 071Devices / Device / intermediateJunction, Diode & Bipolar DevicesHow do junction electrostatics and carrier injection create rectification, gain, and breakdown?
Public packet
DV / 076Devices / Device / intermediateMOS Capacitors & TransistorsHow do gate electrostatics and transport become threshold, current, capacitance, and leakage?
Evidence reviewed
DV / 081Devices / Device / advancedFinFET, GAAFET & CFET LogicHow do gate control, stacking, contacts, parasitics, and variability trade off across scaled architectures?
Evidence reviewed
DV / 086Devices / Device / advancedPower, SiC & GaN DevicesHow do wide-bandgap materials, fields, traps, and thermal paths shape power and RF device limits?
Evidence reviewed
DV / 091Devices / Device / advancedRF & High-Frequency DevicesHow do transport, capacitance, parasitics, fixtures, reference planes, and noise limit high-frequency evidence?
Evidence reviewed
DV / 096Devices / Device / advancedPhotonics & OptoelectronicsHow do photons, carriers, modes, and materials create emission, detection, and modulation?
Evidence reviewed
DV / 101Devices / Device / advancedSensors & MEMSHow do electrical, mechanical, thermal, chemical, or optical transduction paths become a sensor signal?
Source anchored
DV / 106Devices / Device / advancedEmerging & Quantum DevicesWhich state variable stores or transforms information, and what evidence distinguishes a device concept from a product claim?
Source anchored
CS / 111Circuits & Systems / Circuit / intermediateAnalog Circuit PrimitivesHow do bias, gain, feedback, noise, and loading create an analog response?
Evidence reviewed
CS / 116Circuits & Systems / Digital / Verification / intermediateDigital Logic, Timing & Sequential StateHow do logic depth, slew, load, clocking, and state create delay and functional boundaries?
Evidence reviewed
CS / 121Circuits & Systems / Memory / advancedSRAM Cells, Arrays & PeripheryHow do transistor ratios, array context, sensing, and assist shape SRAM stability and access?
Evidence reviewed
CS / 126Circuits & Systems / Memory / advancedDRAM, HBM & Memory HierarchyHow do charge storage, refresh, array organization, and stacked interfaces preserve and move data?
Evidence reviewed
CS / 131Circuits & Systems / Memory / advancedNAND & Emerging Nonvolatile MemoryWhich physical state stores information, how is it switched, and what limits retention and endurance?
Evidence reviewed
CS / 136Circuits & Systems / Circuit / advancedMixed-Signal & Data ConversionHow do sampling, quantization, references, mismatch, and timing become conversion accuracy?
Source anchored
CS / 141Circuits & Systems / EDA / Layout / advancedPower, Clock & On-Chip InterconnectHow do delivery networks, switching activity, parasitics, and topology create integrity and timing limits?
Evidence reviewed
CS / 146Circuits & Systems / Digital / Verification / advancedArchitecture, Accelerators & Compute-in-MemoryHow do data movement, precision, parallelism, and memory placement shape system efficiency?
Source anchored
DVF / 151Design & Verification / Digital / Verification / intermediateHDL, RTL & MicroarchitectureHow is intended cycle-level behavior expressed without hiding reset, latency, and interface contracts?
Public packet
DVF / 156Design & Verification / Digital / Verification / advancedFunctional Verification & Formal MethodsWhich behavior is tested, asserted, covered, or proven, and what remains outside the contract?
Source anchored
DVF / 161Design & Verification / EDA / Layout / intermediateLogic Synthesis & OptimizationHow do RTL, constraints, libraries, and transforms become a gate-level implementation?
Evidence reviewed
DVF / 166Design & Verification / EDA / Layout / advancedFloorplanning, Placement, CTS & RoutingHow do geometry, density, connectivity, power, and clocks become an implementation and its reports?
Evidence reviewed
DVF / 171Design & Verification / EDA / Layout / advancedTiming, Extraction & Signoff LiteracyHow do parasitics, constraints, corners, and analysis assumptions become a timing or verification statement?
Evidence reviewed
DVF / 176Design & Verification / Digital / Verification / advancedDFT, BIST & Design for TestHow is internal state made controllable and observable, and which fault model is actually covered?
Public packet
DVF / 181Design & Verification / EDA / Layout / advancedOpen EDA & Reproducible FlowsCan another person identify the exact source, tool, configuration, artifact, and limitation behind the result?
Evidence reviewed
MP / 186Measurement & Productization / Metrology / Yield / intermediateMetrology & InstrumentationWhat measurand, instrument chain, sampling plan, and calibration support the reported value?
Evidence reviewed
MP / 191Measurement & Productization / Metrology / Yield / intermediateStatistics, DOE & UncertaintyHow much of the observed variation comes from the process, model, sample, or measurement system?
Evidence reviewed
MP / 196Measurement & Productization / Metrology / Yield / advancedProcess Control, Yield & Defect LearningWhich variation signal warrants monitoring, diagnosis, or action without confusing correlation with root cause?
Evidence reviewed
MP / 201Measurement & Productization / Packaging / Test / Reliability / advancedPackaging, Assembly & ChipletsHow do interconnect geometry, bonding, thermal-mechanical stress, and partitioning affect package readiness?
Evidence reviewed
MP / 206Measurement & Productization / Packaging / Test / Reliability / advancedWafer Sort, Final Test & CharacterizationWhich test condition, limit, guardband, and coverage support a product decision?
Public packet
MP / 211Measurement & Productization / Packaging / Test / Reliability / advancedReliability & Failure AnalysisWhich stress, mechanism, acceleration model, and physical evidence support a lifetime or failure claim?
Evidence reviewed
MP / 216Measurement & Productization / Packaging / Test / Reliability / advancedStandards, Traceability & Quality SystemsWhich controlled definition, traceability record, and change history makes the result comparable and auditable?
Source anchored
MP / 221Measurement & Productization / Equipment / Facilities / advancedSafety, Sustainability & Research DataHow are hazards, environmental burdens, data stewardship, and public claims bounded across the lifecycle?
Source anchored
Traverse 4,733 nodes, 10,671 declared edges, three guided slices, and every unsupported bridge without automatic graph completion.
Open the graph ->V131 / COVERAGE & GAP LEDGERInspect all 45 clusters with explicit denominators.Review source metadata, public experiment links, inherited audit states, gap codes, freshness, and the transparent next-audit queue.
Open the ledger ->SOURCE & COVERAGE CONTRACT
A map can be broad without pretending to be complete.
Link first, synthesize originally, preserve provenance, and never imply that a registered source has been fully reviewed when only its metadata or index was inspected.
An official or rights-holder link is registered. Exhaustive review is not implied.
A related lesson, lab, domain page, or replay exists at cluster level.
A related cluster replay exposes data, methods, limits, and evidence links.
PUBLIC BOUNDARY
What this atlas does not claim.
- The taxonomy is a living navigation system, not a claim that SemiAgora has mastered or validated every semiconductor topic.
- No production process recipe, equipment-control instruction, qualified limit, signoff decision, or product ranking is provided.
- No accounts, uploads, payments, confidential files, public research intake, or hidden server solvers are enabled.
- Registered sources may be indexes or metadata records; users must follow the linked rights-holder terms and current document versions.