Sense margin
Bitline differential must survive offset and attenuation before decision time has meaning.
LESSON PACKET / SA-MEM-DEPTH-001
SRAM grows from a cell.
Evidence grows by layer.
Use this packet after the first SRAM write-boundary lesson. The goal is to keep sense amplifier margin, column mux/I/O, read disturb, assist vocabulary, and cache behavior connected without pretending they are the same kind of evidence.
CONCEPT ARC
Do not flatten memory into one number.
SRAM evidence lives at different abstraction layers. A bitline differential is not a controller response, and a cache miss-rate example is not a bitcell characterization. This lesson makes those boundaries explicit.
Column mux and I/O
Words-per-row muxing, shared sense load, and write off-state loading change what reaches the output.
Read disturb
Cell ratio and wordline pulse width move dynamic disturb and read-stability budget in different ways.
Assist taxonomy
Write assist, read assist, energy, coupling, and neighboring-mode penalties need separate evidence.
Cache behavior
SRAM latency becomes architecture-visible only through access pattern, miss rate, and miss penalty.
SIMULATION BUNDLE
Four run cards, one memory spine.
Each promoted object has Explore / Run Card / Export / Methods / Limits / Evidence, so paper-writing users can start from the simulation page without watching the lesson first.
SRAM sense amplifier decision margin
Replay bitline differential, offset sigma, attenuation loss, positive margin, and decision-time interpretation before claiming a sense amplifier can resolve.
11 / 127 mV111.1-332.9 ps
Open simulation ->SRAM column MUX and I/O interactive replay
A browser CSV replay of 864 verified PDK-free ngspice cases connecting mux ratio, pass-device scale, shared sense/I/O load, write-path off-state, transfer efficiency, and output latency.
864423 to 546 ps5030
Open simulation ->SRAM read-disturb sizing
Replay how normalized cell ratio and wordline pulse width change read-disturb peak, read-SNM proxy, and a retained/not-retained budget.
10 / 12187 mV224.7 mV
Open simulation ->SRAM assist taxonomy
Classify baseline write, cell-VDD collapse, wordline boost, negative bitline, and read wordline-underdrive as tradeoff cards instead of recipe settings.
5118 mV64 mV
Open simulation ->Cache behavior replay for SRAM latency intuition
Replay blocked, sequential, strided, random, and conflict-thrashing access patterns with AMAT so SRAM timing stays connected to system-visible latency.
1.52-68 cycles527.37x
Open simulation ->RESEARCH OUTPUTS
What a useful note should produce.
The point is not to add more cards. The point is to produce reusable research artifacts with methods, conditions, non-claims, and next evidence needs attached.
One margin table that separates bitline signal, offset, mux attenuation, and decision time.
Attach this artifact to any future figure, slide, or article that uses the memory-depth pack.
One column-interface table that keeps local differential, shared differential, common-mode, output timing, and non-claims together.
Attach this artifact to any future figure, slide, or article that uses the memory-depth pack.
One read-disturb sizing table that keeps SNM proxy and dynamic disturb separate.
Attach this artifact to any future figure, slide, or article that uses the memory-depth pack.
One assist tradeoff table that names read/write/energy/reliability consequences.
Attach this artifact to any future figure, slide, or article that uses the memory-depth pack.
One AMAT note that explains why cache behavior is system evidence, not transistor evidence.
Attach this artifact to any future figure, slide, or article that uses the memory-depth pack.
BOUNDARIES
Useful depth, still static.
No live SPICE, arbitrary HDL, trace upload, SRAM macro signoff, ATE programming, qualification, or product-release workflow is enabled. These are educational precomputed replays.
Next best memory additions
After this pack, memory can deepen toward DRAM retention upgrades, array banking vocabulary, compiler boundary cards, and measured-data replacements when rights are clean.
Open Memory domain ->