1.52-68 cyclesAMAT rangeUNKNOWNInspect metric contract
5Access patternsUNKNOWNInspect metric contract
27.37xRandom/block ratioUNKNOWNInspect metric contract
SIMULATION / SA-MEM-DEPTH-CACHE-001
Cache behavior replay for SRAM latency intuition
Cache Replay
Replay blocked, sequential, strided, random, and conflict-thrashing access patterns with AMAT so SRAM timing stays connected to system-visible latency.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Compare blocked access against random pointer walking.
- Read miss rate and miss penalty before interpreting AMAT.
- Keep architecture-visible latency separate from bitcell or sense-amplifier timing.
RUN CARD
Conditions before conclusions.
The page replays saved AMAT cases. It does not accept user traces or run a processor simulation.
Primary knobs
- Pattern: blocked, sequential, strided, random, conflict thrash
- L1 miss rate and L2 local miss rate
- L2 hit time and memory penalty
- AMAT formula from public course notes
Saved outputs
- AMAT cycles
- cache-friendly/memory-bound label
- miss-rate sensitivity
- system boundary note
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/sram-cache-behavior-replay-web-v1.json
Open file ->Model script
/data/sram_memory_depth_models.mjs
Open file ->Model card
/data/sram-memory-depth-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Use the recursive AMAT expression for a two-level hierarchy.
Keep this method attached when reusing the figure or metric.
Separate access pattern from cache hit time, miss rate, and miss penalty.
Keep this method attached when reusing the figure or metric.
State that system-level memory behavior is not transistor-level SRAM evidence.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
This replay uses synthetic workload patterns and educational cycle counts, not measured CPU performance.
Carry this boundary into any derivative note, paper draft, or slide.
It connects SRAM/cache vocabulary to memory hierarchy behavior; it does not model a specific processor, cache controller, compiler, or DRAM timing.
Carry this boundary into any derivative note, paper draft, or slide.
The model ignores coherence traffic, prefetching, write policy, TLB effects, bank conflicts, and queueing.
Carry this boundary into any derivative note, paper draft, or slide.
System-level cache conclusions must not be used as evidence for a transistor-level SRAM macro without separate timing data.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
The dataset records five access-pattern cases.
SA-MEM-DEPTH-CACHE-001
Verification checks that higher miss rates increase AMAT.
SA-MEM-DEPTH-CACHE-001
The model card marks the replay as synthetic and trace-free.
SA-MEM-DEPTH-CACHE-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
UCLA eScholarship SRAM sense amplifier thesisPublic thesis used for offset, attenuation, control-timing, and sense-amplifier vocabulary.Grossar et al. SRAM read stability and write-abilityPublic paper used for read-stability, write-ability, SNM, and N-curve vocabulary.NVIDIA reverse write assist and SRAM VMIN paperPublic paper used to anchor assist, reverse assist, VMIN, guardband, and canary vocabulary.CS61C average memory access time notesPublic course note used for hit time, miss rate, miss penalty, and AMAT vocabulary.
Public execution boundary
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