864verified transient casesUNKNOWNInspect metric contract
423 to 546 psmux ratio latency medianUNKNOWNInspect metric contract
503passing rowsUNKNOWNInspect metric contract
0live server runsUNKNOWNInspect metric contract
SIMULATION / SA-MEM-017
SRAM column MUX and I/O interactive replay
Column MUX/I/O
A browser CSV replay of 864 verified PDK-free ngspice cases connecting mux ratio, pass-device scale, shared sense/I/O load, write-path off-state, transfer efficiency, and output latency.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Filter mux ratio and shared sense/I/O load to see why a wider words-per-row mux can trade area for latency and input attenuation.
- Compare clean and leaky write-path off-state rows to separate read-mode loading from write-driver function.
- Watch transfer efficiency, shared differential, common-mode, unselected disturbance, and output latency as separate observables.
- Use the source catalog and model card before reusing any row in a paper note or slide.
BROWSER INTERACTIVE LAB
Filter the saved CSV. Inspect matching replay rows.
No server solver is running here. The browser filters a precomputed table and redraws the plot locally.
Loading replay rowsReading the saved CSV in this browser.
latency mux to dout50 psshared diff sample mvtransfer efficiency
Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.
n/alatency mux to dout50 ps
n/ashared diff sample mv
n/atransfer efficiency
Change one or more controls to find a saved row. No unrelated CSV value is substituted.
| case id | vdd v | mux ratio | bitline depth | mux tx scale | sense load ff | write path state | shared diff sample mv | transfer efficiency | latency mux to dout50 ps | label |
|---|---|---|---|---|---|---|---|---|---|---|
| Loading saved replay rows... | ||||||||||
RUN CARD
Conditions before conclusions.
The browser filters saved CSV rows and redraws the local plot. It does not run ngspice, accept uploads, ingest PDK/model decks, or optimize SRAM circuits on a server.
Primary knobs
- vdd_v
- mux_ratio
- bitline_depth
- mux_tx_scale
- sense_load_ff
- write_path_state
Saved outputs
- local_diff_sample_mv
- shared_diff_sample_mv
- transfer_efficiency
- shared_common_mode_sample_v
- latency_mux_to_dout50_ps
- unselected_disturb_mv
- energy_fj
- label
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Interactive CSV rows
/data/sram-column-mux-io-v75.csv
Open file ->Web result JSON
/data/sram-column-mux-io-web-v1.json
Open file ->Source catalog CSV
/data/sram-column-mux-io-source-catalog-v1.csv
Open file ->Model card
/data/sram-column-mux-io-model-card-v1.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Generate a deterministic 864-case transient grid over VDD, mux ratio, selected bitline depth, mux pass-device scale, shared sense/I/O load, and write-path off-state.
Keep this method attached when reusing the figure or metric.
Measure local bitline differential, shared sense differential, transfer efficiency, common-mode, output 50 percent crossing, unselected disturbance, energy, and outcome label.
Keep this method attached when reusing the figure or metric.
Independently reparse decks, raw waveforms, topology tokens, parameter grid, metrics, labels, and artifact hashes before promoting the browser replay.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
The fixture uses generic Level-1 MOS devices, lumped loads, and effective pass-device behavior.
Carry this boundary into any derivative note, paper draft, or slide.
It is not calibrated macro timing, foundry evidence, silicon evidence, yield qualification, reliability signoff, or a product comparison.
Carry this boundary into any derivative note, paper draft, or slide.
No live server solver execution or uploaded design/netlist ingestion; the public page filters saved rows only.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
Research QA passed 15/15 with 20 source records, 20 controlled claims, and 15 misconception corrections.
SA-MEM-017
Primary fixture QA passed 13/13 and independent no-import verification passed 10/10.
SA-MEM-017
The public CSV is generated from the verified 864-row metric table and keeps the same measurement contract.
SA-MEM-017
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
OpenRAM architecture documentationAnchors the SRAM macro block boundary around decoders, column mux, precharge, sense amplifiers, write drivers, and control logic.OpenRAM column mux moduleOpen-source reference for treating column muxing as selected pass devices between local bitlines and shared column circuitry.OpenRAM: An Open-Source Memory CompilerPublic compiler paper for SRAM module context; SemiAgora uses original teaching data and does not copy figures.CACTI 7 memory modeling toolAnchors memory timing and array-peripheral tradeoff vocabulary at an analytical-tool level.ngspice simulator documentationOpen simulator used for the PDK-free transient replay fixture.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.