01 / Local Pair
BL and BR develop a selected-cell differential before column select.
LESSON PACKET / SA-MEM-017
Column selection is analog.
The output is only the last observable.
This packet turns the SRAM column mux from a small diagram block into a measurable interface: local bitline differential, shared sense pair, common-mode, write-path off-state loading, and output timing stay separate.
CONCEPT ARC
The sense amplifier reads what the column path delivers.
Words-per-row muxing saves shared sense and write circuitry, but it adds pass resistance, shared capacitance, possible write-path loading, and timing consequences. This lesson keeps those consequences visible before any macro-level claim.
02 / Column MUX
Pass devices translate that local differential into SBL and SBR with finite transfer efficiency.
03 / Shared I/O
Sense load, output buffering, and write off-state loading affect the observable data timing.
04 / Evidence Rule
Mux ratio, load, state, and extraction rule travel with every plotted number.
EVIDENCE GRID
864 cases, one measurement contract.
Primary fixture QA passed 13/13; independent verification passed 10/10. The public lab reads the same verified metric table.
864
Use this number only with the run card, method, and limits attached.
423 to 546 ps
Use this number only with the run card, method, and limits attached.
503
Use this number only with the run card, method, and limits attached.
0
Use this number only with the run card, method, and limits attached.
BOUNDARIES
Useful SRAM depth, still a teaching fixture.
No final video is claimed on this page. The verified slide deck exists, but public media release still needs uninterrupted human review. The simulation is precomputed generic Level-1/lumped-load evidence, not macro timing or silicon evidence.
Best next use
Open the simulation page, filter the CSV, then write a short evidence note that separates mux ratio, shared load, write off-state, transfer efficiency, latency, and the non-claims.
Open SA-MEM-017 simulation ->