0.76206Highest placement scoreUNKNOWNInspect metric contract
SRAM / edge always-onBest caseUNKNOWNInspect metric contract
24 casesSweep rowsUNKNOWNInspect metric contract
SIMULATION / SA-MEM-003-MEMORY-HIERARCHY-PLACEMENT-001
Memory hierarchy placement map
Hierarchy Map
Replay SRAM, DRAM, HBM, SCM, NAND, and MRAM across workload weights to choose the right evidence question.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Pick the workload first, then compare memory technologies.
- Separate latency, bandwidth, capacity, endurance, and energy movement instead of asking for one best memory.
- Use the placement score as a discussion scaffold, not a product benchmark.
RUN CARD
Conditions before conclusions.
This page replays saved memory-placement data and does not run traces, simulators, or vendor benchmarks.
Primary knobs
- Technology label
- Workload label
- Weighting assumptions
Saved outputs
- Latency score
- Capacity score
- Endurance score
- Placement score
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/memory-hierarchy-placement-map-web-v1.json
Open file ->Dataset CSV
/data/memory-hierarchy-placement-map-v64.csv
Open file ->v64 deep simulation summary CSV
/data/v64-deep-simulations-summary.csv
Open file ->v64 deep model script
/data/v64_deep_semiconductor_sims.mjs
Open file ->v64 deep model card
/data/v64-deep-simulations-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Each technology receives normalized latency, bandwidth, capacity, and endurance scores.
Keep this method attached when reusing the figure or metric.
Each workload applies different weights to those scores.
Keep this method attached when reusing the figure or metric.
Placement score is a weighted teaching index used to choose the next evidence question.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No cost model, product spec, procurement guidance, workload trace, or benchmark result is included.
Carry this boundary into any derivative note, paper draft, or slide.
No claim is made that one technology is universally superior.
Carry this boundary into any derivative note, paper draft, or slide.
Real architecture work needs measured workload locality, latency, bandwidth, energy, capacity, and software stack evidence.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
v64 deep results store every technology/workload score row.
SA-MEM-003-MEMORY-HIERARCHY-PLACEMENT-001
CSV export preserves the placement table.
SA-MEM-003-MEMORY-HIERARCHY-PLACEMENT-001
The result helps decide whether the next study should be SRAM, DRAM/HBM, SCM, NAND, MRAM, or CIM.
SA-MEM-003-MEMORY-HIERARCHY-PLACEMENT-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
Ramulator2External MIT-licensed DRAM/HBM simulator reference; v64 pages use original teaching data.DRAMsim3External MIT-licensed DRAM timing and thermal simulator reference.IEEE IRDSRoadmap source spine for memory hierarchy and emerging memory vocabulary.Google Security RowHammer research notePublic context for RowHammer as a DRAM charge-leakage, refresh, and security-evidence topic.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.