500 -> 125 psSense delayUNKNOWNInspect metric contract
20 / 40 / 80 uACell currentUNKNOWNInspect metric contract
100 mVSense thresholdUNKNOWNInspect metric contract
SIMULATION / SRAM_BITLINE_SENSE_001
SRAM bitline differential sensing
Bitline Sense
Replay a lumped-bitline model that connects cell current, bitline capacitance, and sense-enable timing.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Increase cell current and observe the inverse delay trend.
- Keep the 100 fF bitline capacitance fixed while reading the timing marker.
- Use the result to decide when a sense amplifier may safely enable.
RUN CARD
Conditions before conclusions.
The current page replays saved current-source cases and does not run a new circuit job.
Primary knobs
- Cell current: 20 uA, 40 uA, 80 uA
- Bitline capacitance: 100 fF
- Sense differential: 100 mV
- Identity: t = C_BL * DeltaV / I_cell
Saved outputs
- differential waveform
- sense time
- analytical cross-check
- delay ordering
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/bitline-sense-web-v1.json
Open file ->Weak current netlist
/data/sense-weak.spice
Open file ->Nominal current netlist
/data/sense-nominal.spice
Open file ->Strong current netlist
/data/sense-strong.spice
Open file ->Package script
/data/package_bitline_sense.py
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Hold capacitance and threshold constant while changing current.
Keep this method attached when reusing the figure or metric.
Measure time to 100 mV differential.
Keep this method attached when reusing the figure or metric.
Cross-check ngspice results against the lumped C * V / I identity.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No transistor-level 6T nonlinearity, distributed column RC, mismatch, noise, or latch sense amplifier is included.
Carry this boundary into any derivative note, paper draft, or slide.
The 100 mV marker is a teaching threshold, not a characterized production specification.
Carry this boundary into any derivative note, paper draft, or slide.
This model explains bitline development, not full SRAM read access timing.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
Verification records three converged cases and monotonic delay with current.
SRAM_BITLINE_SENSE_001
The maximum analytical error is preserved in the dataset.
SRAM_BITLINE_SENSE_001
All source netlists and the package script are downloadable.
SRAM_BITLINE_SENSE_001
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.