What changed on wafer
Surface state, contact clean, anneal window, contact area, film continuity, CD, stress, or CMP topography.
PROCESS TO DEVICE TO CIRCUIT CHAINS
Do not stop at the module.
Follow the downstream metric.
Rights-clean chain candidates for connecting process changes to device metrics, circuit delay, memory margin, yield evidence, and measured replacement slots.
CHAIN DISCIPLINE
Each process claim must say what it changes next.
A process module becomes useful to device, circuit, memory, EDA, and yield readers only when the handoff metric is explicit and replaceable with measured evidence.
What electrical primitive moved
Contact resistance, sheet resistance, Vt, DIBL, mobility, capacitance, leakage, or variability proxy.
What timing or margin changed
Ring oscillator delay, FO4 delay, bitline RC delay, SRAM read margin, STA slack, IR drop, or sense timing.
What replaces the proxy
TLM, sheet-R, CD-SEM, C-V, Id-Vg, ring oscillator, SRAM table, wafer map, or uncertainty record.
PROMOTED BROWSER CHAIN
Contact resistance now has a downstream timing surface.
The v72 promoted chain uses saved CSV rows to connect contact-related process knobs to Rc/Rsd proxies, ring oscillator delay proxy, and SRAM bitline delay proxy.
Contact clean/silicide/contact anneal -> Rc/Rsd -> ring oscillator/bitline delay
No qualified contact module claim; browser table is an original proxy sweep.
What real evidence should replace
- TLM contact resistance
- sheet resistance
- ring oscillator delay
- SRAM bitline delay
CHAIN BACKLOG
The next simulations should be coupled, not isolated.
Each card below is a candidate for a future precomputed browser lab. Promote only when source anchors, original data, measured replacement slots, and limits are ready.
O2/O3 treatment -> ALD nucleation -> EOT/cap/leakage proxy
No material-specific recipe, gas ratio, or equipment-control instruction.
Replace proxy with: contact angle / incubation cycles / film thickness / C-V leakage
Anneal -> activation/diffusion -> Rs/Vt -> FO4/SRAM Vmin proxy
No implant or RTA recipe; all values remain teaching proxies unless replaced.
Replace proxy with: sheet resistance / SIMS junction profile / Id-Vg / FO4 delay
Etch CD/LER -> Lg/Weff -> DIBL/Vt variability -> inverter delay/SRAM SNM
No etch process setting or foundry signoff rule.
Replace proxy with: CD-SEM / LER sigma / Id-Vg split / SNM or delay table
Stress liner/source-drain stressor -> mobility -> Idsat -> path delay
No proprietary stress module recipe or calibrated TCAD claim.
Replace proxy with: Raman stress / mobility extraction / Idsat / timing proxy
Contact clean/silicide/contact anneal -> Rc/Rsd -> ring oscillator/bitline delay
No qualified contact module claim; browser table is an original proxy sweep.
Replace proxy with: TLM contact resistance / sheet resistance / ring oscillator delay / SRAM bitline delay
CMP dishing/erosion -> metal R/C -> STA slack/IR-drop proxy
No product release or signoff result.
Replace proxy with: dishing metrology / sheet resistance / extracted RC / timing slack
Litho focus/exposure -> CD distribution -> timing and yield-tail risk
No lithography recipe or mask-specific rule.
Replace proxy with: focus-exposure matrix / CD uniformity / timing distribution / yield pareto
Plasma etch UQ -> depth/profile uniformity -> profile risk -> yield risk
No optimizer recommendation or process setting.
Replace proxy with: etch depth map / profile angle / selectivity / defect or excursion labels
Wet clean/native oxide -> interface state -> TLM/Rc -> circuit delay
No chemical sequence recipe or queue-time operating procedure.
Replace proxy with: surface oxide / contact angle / TLM / ring oscillator
GAA nanosheet geometry -> electrostatics/cap -> SRAM/cell delay proxy
No calibrated foundry architecture claim.
Replace proxy with: geometry split / C-V / Id-Vg / cell delay or read margin
Forksheet/CFET stack choice -> parasitic load -> PPA sensitivity
No private library or node-specific PPA claim.
Replace proxy with: parasitic extraction / standard-cell delay / area / power
Hybrid bonding surface/mechanical readiness -> continuity and thermal-risk proxy
No qualification approval or assembly recipe.
Replace proxy with: roughness / particle count / bond void inspection / thermal resistance
Inline metrology uncertainty -> guardband decision -> false-pass/false-fail risk
No private wafer data or product disposition.
Replace proxy with: repeatability / reproducibility / sample plan / escape/yield labels
Source/drain stress plus contact co-optimization -> Idsat/Rsd -> FO4/bitline delay
No module recipe or calibrated DTCO result.
Replace proxy with: stress metrology / Rc / Idsat / FO4 or bitline delay
SOURCE SPINE
Use public sources to define the vocabulary, then build original rows.
The sources below anchor terminology and scope. SemiAgora does not mirror papers or convert public reading into a manufacturing procedure.
NIST metrology and process-control uncertainty
Anchors why inline measurements and uncertainty must be kept attached when process conditions change.
Open source ->TSMC design-technology co-optimization
Anchors the process, device, and design co-optimization vocabulary used for downstream handoffs.
Open source ->imec contact resistance challenge
Anchors contact resistance as a scaling limiter that belongs in device and circuit consequence chains.
Open source ->ALD on MoS2 with ozone or water oxidant
Anchors ozone as a surface/ALD nucleation teaching topic while preserving material and process boundaries.
Open source ->UV ozone pretreatment for ALD nucleation
Anchors surface pretreatment, nucleation, and film-continuity vocabulary for future chain replacements.
Open source ->FinFET stress-engineering review
Anchors stress, mobility, and device-performance coupling for future process-to-device chains.
Open source ->GAA nanosheet transistor review
Anchors gate-all-around geometry, electrostatics, and capacitance vocabulary for future chains.
Open source ->Hybrid bonding review
Anchors bonding-surface and package-integration evidence for post-fab chain candidates.
Open source ->PUBLIC BOUNDARY
Strong chain thinking, no hidden factory workflow.
The chain route exists to organize study and simulation backlog. It is not a facility, process, or product-decision system.
Precomputed educational data only.
Keep this statement with any figure, row, or slide derived from the chain backlog.
No live server solver execution.
Keep this statement with any figure, row, or slide derived from the chain backlog.
No process recipe, gas-ratio recommendation, equipment-control instruction, or endpoint-control workflow.
Keep this statement with any figure, row, or slide derived from the chain backlog.
No PDK, NDA, proprietary, or paid source text is redistributed.
Keep this statement with any figure, row, or slide derived from the chain backlog.
No measured-silicon, qualification, yield-release, or signoff claim.
Keep this statement with any figure, row, or slide derived from the chain backlog.