One module.
Four decisions.

Check wafer queue time, preclean state, O2/O3/plasma exposure record, chamber pressure, purge timing, wafer temperature, byproduct removal, particle log, and safety boundary.

Study nucleation delay, growth-per-cycle saturation, film density, interface state proxy, leakage risk, conformality, and throughput tradeoff.

Connect pretreatment to dielectric quality, contact/via resistance, interface traps, downstream thermal budget, contamination risk, and module handoff criteria.

Track thickness nonuniformity, particle adders, leakage tail, lot split delta, metrology uncertainty, and excursion rules before claiming improvement.

Check target condition, chamber base pressure, power or rate setpoint record, wafer rotation, shield/seasoning state, thickness monitor, and particle log.

Study deposition rate, step coverage, film stress, sheet resistance, adhesion, composition drift, target aging, and uniformity tradeoff.

Connect film continuity to contact resistance, barrier/seed readiness, via fill, electromigration margin, CMP burden, and package/interconnect parasitics.

Track thickness map, Rs map, void/open risk, stress-related defects, chamber matching, and lot-to-lot drift.

Check reticle, resist coat/bake state, focus/exposure recipe record, alignment marks, track status, develop state, and inspection hold points.

Study process window, CD bias, overlay residual, focus sensitivity, exposure latitude, LER, and resist/process interaction.

Connect CD/overlay to transistor width, contact landing, via enclosure, BEOL capacitance, SRAM cell rules, and DTCO design margins.

Track CD distribution, overlay vectors, wafer/location signature, missing/bridging defect risk, rework boundary, and guardband choice.

Check approved chamber, source, bias, matching, gas, vacuum, wall-history, endpoint, mask-retention, damage, interlock, maintenance, and safety records without treating a teaching proxy as an equipment or wafer action.

Separate ion access, reactive-neutral availability, passivation retention, chemical and physical removal, synergy, mask erosion, selectivity, damage, transport, profile control, stability, and model discrepancy before proposing a physical study.

Connect owned vacuum and plasma state to material stack, feature access, mask and stop layers, profile evolution, CD, device impact, residue, downstream clean, PTCO/DTCO, and replacement-evidence review.

Track calibrated rate, selectivity, CD, depth, sidewall, roughness, damage, charging, endpoint, chamber matching, repeatability, wafer signature, Gauge R&R, false alarm, escape risk, and accountable disposition evidence.

Check species, dose, energy, tilt, wafer temperature, anneal ramp/soak/cool-down record, queue time, and contamination boundary.

Study activation, diffusion, residual damage, junction leakage, sheet resistance, contact/silicide readiness, contact resistance, and short-channel control.

Connect thermal budget to gate stack, spacers, strain, silicide, contact resistance, Vt distribution, SRAM assist margin, FO4 delay, and bitline delay.

Track Rs map, Vt distribution, leakage tail, parametric binning, monitor-structure correlation, and confidence for release gates.

Check pad/slurry/conditioner state, pressure, platen speed, endpoint, clean recipe record, consumable lifetime, scratch log, and hold criteria.

Study removal rate, selectivity, dishing, erosion, planarity, pattern-density sensitivity, residue, and post-CMP clean effectiveness.

Connect topography to lithography focus, via/contact landing, BEOL resistance/capacitance, hybrid bonding readiness, and packaging reliability.

Track dishing/erosion maps, scratch counts, open/short risk, thickness-control SPC, and pattern-density correlation.

Check chemical bath age, concentration record, rinse/dry state, queue time, wafer carrier cleanliness, particle monitor, and chemical safety boundary.

Study particle removal, metal/organic residue risk, oxide regrowth, surface termination, contact angle, and defect tradeoff.

Connect surface condition to ALD nucleation, contact resistance, gate-stack interface, etch residue removal, and wafer bonding readiness.

Track particle adders, residue defect pareto, contamination monitor trend, leakage tail, and excursion containment.

Check calibration state, sampling plan, lot, wafer, die, device, measurement, test, recipe version, tool health, alarm, hold, release, disposition, and data-integrity records; a teaching browser cannot authorize an action.

Study measurement repeatability, bias, sensitivity, response-model and monitor-structure relevance, then separate variation family, measurement-system contribution, device-model transfer, circuit, reliability and test context, spatial correlation, genealogy, and uncertainty before proposing causal attribution.

Connect metrology and owned process-module outputs to process control, device characterization, compact-model validation, circuit guardbands and margin, reliability screens, test, design-rule review, and yield evidence through explicit interfaces and accountable PTCO or DTCO review.

Track control charts, capability indices, denominator, sampling, map transforms, defect pareto and bin taxonomy, lot-wafer-die-device genealogy, false-alarm and escape risk, model discrepancy, confidence, change control, and human disposition governance.

Check approved gauge, MFC, valve, pump, gas-panel, foreline, abatement, interlock, chamber-history, leak/outgassing, maintenance, and safety records without treating a teaching proxy as an equipment action.

Separate admitted load, wall release, conductance, nominal pump capability, effective pumping, chamber/foreline inventory, settling, residence, distribution, and measurement uncertainty before proposing a physical study.

Connect owned vacuum and delivery evidence to wall state, plasma source and sheath behavior, wafer-facing distributions, deposition or etch response, contamination, throughput, PTCO/DTCO, and downstream module requirements.

Track calibrated pressure and flow distributions, transient signatures, chamber matching, repeatability, drift, Gauge R&R, false alarms, escape risk, wafer correlation, and accountable review gates.