Educational role path

Circuit and memory engineering

Trace SRAM cell, read, sensing, array, control, and test behavior while preserving metric conditions and evidence limits.

Levels: 3
Checkpoints: 6
Artifact tasks: 12

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Competency level

Foundation

Name the variables, units, artifacts, and evidence classes required to read the role path.

1.1

Map SRAM cell operation

Map hold, read, and write behavior to cell nodes, access conditions, and visible stability metrics.

Prerequisite: Start here
Evidence boundary: A cell teaching figure or static metric is not a full memory qualification.

Public artifact tasks

lessonSRAM memory depthLocate cell, array, peripheral, reliability, and test layers.labSRAM SNM labInspect the static-margin metric and conditions.

1.2

Identify read metrics

Identify read disturb, bitline development, delay, and sensing conditions in a bounded read replay.

Prerequisite: Map SRAM cell operation
Evidence boundary: The read replay is not extracted PVT signoff or silicon timing.

Public artifact tasks

labSRAM read labTrace a read event and record its displayed conditions.simulationSRAM read transientCompare timing and bitline states without changing the model contract.

Competency level

Cross-domain practice

Trace and compare bounded public replays across at least one engineering handoff.

2.1

Compare sensing margin

Compare two bitline sensing states and explain the decision-margin change using the displayed variables.

Prerequisite: Identify read metrics
Evidence boundary: Sensing margin in the replay does not certify a sense amplifier or array.

Public artifact tasks

labBitline sensing labRecord the differential and decision condition.simulationSRAM bitline sensingCompare fixed sensing states.

2.2

Trace array control and test

Trace one request through controller behavior and a bounded BIST fault model while naming what remains untested.

Prerequisite: Compare sensing margin
Evidence boundary: A public protocol or BIST replay does not establish production test coverage.

Public artifact tasks

labSRAM controller labFollow one protocol trace.labSRAM BIST labRelate one fault model to the March sequence.

Competency level

Evidence-ready

Construct an inspectable evidence record with limitations, stop conditions, and replacement needs.

3.1

Evaluate a margin claim

Evaluate a margin claim by recording metric definition, conditions, evidence class, and missing corner coverage.

Prerequisite: Trace array control and test
Evidence boundary: A metric under one condition cannot stand in for full variation and corner evidence.

Public artifact tasks

simulationSRAM static noise marginInspect the public metric contract.referenceEvidence guideClassify the result without upgrading its evidence state.

3.2

Construct a memory handoff

Construct a cell-to-array-to-test handoff with prerequisites, stop conditions, and measured-replacement slots.

Prerequisite: Evaluate a margin claim
Evidence boundary: The handoff is a research structure and not a design, test, or signoff credential.

Public artifact tasks

workspaceEvidence provenanceTrace the artifact and release lineage.sourceSource policyCheck whether the source supports the intended statement.

Role boundary

Evidence first. Career promises stay out.

This path uses original and public teaching artifacts; it does not provide a production memory compiler, timing signoff, or yield prediction.

Role paths are educational navigation. They do not certify competence, promise employment, rank candidates, or represent employer acceptance.

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